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M62371GP 数据表(PDF) 2 Page - Renesas Technology Corp |
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M62371GP 数据表(HTML) 2 Page - Renesas Technology Corp |
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2 / 9 page ![]() M62371GP REJ03D0880-0201 Rev.2.01 Dec 27, 2007 Page 2 of 8 Pin Arrangement M62371GP 36 35 34 33 32 31 30 29 AO35 AO34 AO33 AO32 VSS2 VDD2 C1 AO31 VCC AO30 28 27 26 AO29 AO28 25 1 2 3 4 5 6 7 8 DI CLK LD Do GND C0 VSS1 AO12 VDD1 AO13 9 10 11 AO14 AO15 12 (Top view) Outline: 48P6D-A Pin Description Pin No. Pin Name Function 1 DI Serial data input terminal to input 16-bit long serial data 4 DO Terminal to output MSB data of 16-bit shift register 2 CLK Shift clock input terminal. Input signal at DI pin is input to 16-bit shift register at rise of shift clock pulse 3 LD When H-level signal is input to this terminal, the value stored in 16-bit shift register is loaded in decoder and D/A converter output register. 38 to 48 AO1 to AO11 9 to 28 AO12 to AO31 33 to 37 AO32 to AO36 8-bit D/A converter output terminal 29 VCC Power supply terminal 5 GND GND terminal 6 C0 Data select signal input terminal 1 for channel No.31 through 36 30 C1 Data select signal input terminal 2 for channel No.31 through 36 8 VDD1 Upper reference voltage input terminal and power supply to operational amplifier for channel No.1 through 24 7 VSS1 Lower reference voltage input terminal for channel No.1 through 24 31 VDD2 Upper reference voltage input terminal and power supply to operational amplifier for channel No.25 through 36 32 VSS2 Lower reference voltage input terminal for channel No.25 through 36 |
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