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M38043FEHKP 数据表(PDF) 66 Page - Renesas Technology Corp |
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M38043FEHKP 数据表(HTML) 66 Page - Renesas Technology Corp |
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66 / 116 page  Rev.1.01 Jan 25, 2005 page 66 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Fig. 64 START/STOP condition detecting timing diagram START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 64, 65, and Table 11. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL re- lease time, setup time, and hold time (see Table 11). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 11, the BB flag set/ reset time. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “I2CIRQ” occurs to the CPU. Table 11 START condition/STOP condition detecting conditions Note: Unit : Cycle number of internal clock φ SSC value is the decimal notation value of the START/STOP condi- tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2C START/ STOP condition control register is set to “1816” at φ = 4 MHz. Fig. 65 STOP condition detecting timing diagram SCL release time Standard clock mode High-speed clock mode 4 cycles (1.0 µs) 2 cycles (0.5 µs) 2 cycles (0.5 µs) 3.5 cycles (0.875 µs) SSC value + 1 2 SSC value + 1 2 SSC value –1 2 Setup time Hold time BB flag set/ reset time SSC value + 1 cycle (6.25 µs) cycle < 4.0 µs (3.125 µs) cycle < 4.0 µs (3.125 µs) + 2 cycles (3.375 µs) Hold time Setup time SCL SDA BB flag SCL release time BB flag set time Hold time Setup time SCL SDA BB flag SCL release time BB flag reset time |
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