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M38043FEHKP 数据表(PDF) 108 Page - Renesas Technology Corp

部件名 M38043FEHKP
功能描述  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PDF  116 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M38043FEHKP 数据表(HTML) 108 Page - Renesas Technology Corp

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Rev.1.01
Jan 25, 2005
page 108 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
Note : When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
Table 30 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Max.
Symbol
Unit
Typ.
Min.
250
320
500
120
150
240
120
150
240
70
90
100
32
40
50
500
650
1000
200
260
400
200
260
400
100
130
200
100
130
150
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
4.5
≤VCC≤5.5 V
4.0
≤VCC<4.5 V
2.7
≤VCC<4.0 V
Serial I/O1, serial I/O3
clock input cycle time (Note)
Serial I/O1, serial I/O3
clock input “H” pulse width (Note)
Serial I/O1, serial I/O3
clock input “L” pulse width (Note)
Serial I/O1, serial I/O3
clock input setup time
Serial I/O1, serial I/O3
clock input hold time
Serial I/O2
clock input cycle time
Serial I/O2
clock input “H” pulse width
Serial I/O2
clock input “L” pulse width
Serial I/O2
clock input setup time
Serial I/O2
clock input hold time
tC(SCLK1), tC(SCLK3)
tWH(SCLK1), tWH(SCLK3)
tWL(SCLK1), tWL(SCLK3)
tsu(RxD1-SCLK1),
tsu(RxD3-SCLK3)
th(SCLK1-RxD1),
th(SCLK3-RxD3)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)



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