M38047FEHKP datasheet(31/116 Pages) RENESAS

31 / 116 page

Rev.1.01

Jan 25, 2005

page 31 of 114

REJ03B0131-0101Z

3804 Group (Spec. H)

q16-bit Timer

The timer Z is a 16-bit timer. When the timer reaches “000016”, an

underflow occurs at the next count pulse and the corresponding

timer latch is reloaded into the timer and the count is continued.

When the timer underflows, the interrupt request bit corresponding

to the timer Z is set to “1”.

When reading/writing to the timer Z, perform reading/writing to

both the high-order byte and the low-order byte. When reading the

timer Z, read from the high-order byte first, followed by the low-or-

der byte. Do not perform the writing to the timer Z between read

operation of the high-order byte and read operation of the low-or-

der byte. When writing to the timer Z, write to the low-order byte

first, followed by the high-order byte. Do not perform the reading

to the timer Z between write operation of the low-order byte and

write operation of the high-order byte.

The timer Z can select the count source by the timer Z count

source selection bits of timer Y, Z count source selection register

(bits 7 to 4 at address 000F16).

Timer Z can select one of seven operating modes by setting the

timer Z mode register (address 002A16).

(1) Timer mode

qMode selection

This mode can be selected by setting “000” to the timer Z operat-

ing mode bits (bits 2 to 0) and setting “0” to the timer/event

counter mode switch bit (b7) of the timer Z mode register (address

002A16).

qCount source selection

In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/

128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as

the count source.

In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/

512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count

source.

qInterrupt

When an underflow occurs, the INT0/timer Z interrupt request bit

(bit 0) of the interrupt request register 1 (address 003C16) is set to

“1”.

qExplanation of operation

During timer stop, usually write data to a latch and a timer at the

same time to set the timer value.

The timer count operation is started by setting “0” to the timer Z

count stop bit (bit 6) of the timer Z mode register (address

002A16).

When the timer reaches “000016”, an underflow occurs at the next

count pulse and the contents of timer latch are reloaded into the

timer and the count is continued.

When writing data to the timer during operation, the data is written

only into the latch. Then the new latch value is reloaded into the

timer at the next underflow.

(2) Event counter mode

qMode selection

This mode can be selected by setting “000” to the timer Z operat-

ing mode bits (bits 2 to 0) and setting “1” to the timer/event

counter mode switch bit (bit 7) of the timer Z mode register (ad-

dress 002A16).

The valid edge for the count operation depends on the CNTR2 ac-

tive edge switch bit (bit 5) of the timer Z mode register (address

002A16). When it is “0”, the rising edge is valid. When it is “1”, the

falling edge is valid.

qInterrupt

The interrupt at an underflow is the same as the timer mode’s.

qExplanation of operation

The operation is the same as the timer mode’s.

Set the double-function port of CNTR2 pin and port P47 to input in

this mode.

Figure 26 shows the timing chart of the timer/event counter mode.

(3) Pulse output mode

qMode selection

This mode can be selected by setting “001” to the timer Z operat-

ing mode bits (bits 2 to 0) and setting “0” to the timer/event

counter mode switch bit (b7) of the timer Z mode register (address

002A16).

qCount source selection

In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/

128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as

the count source.

In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/

512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count

source.

qInterrupt

The interrupt at an underflow is the same as the timer mode’s.

qExplanation of operation

The operation is the same as the timer mode’s. Moreover the

pulse which is inverted each time the timer underflows is output

from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of

the timer Z mode register (address 002A16) is “0”, the output starts

with “H” level. When it is “1”, the output starts with “L” level.

sPrecautions

The double-function port of CNTR2 pin and port P47 is automati-

cally set to the timer pulse output port in this mode.

The output from CNTR2 pin is initialized to the level depending on

CNTR2 active edge switch bit by writing to the timer.

When the value of the CNTR2 active edge switch bit is changed,

the output level of CNTR2 pin is inverted.

Figure 27 shows the timing chart of the pulse output mode.

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