HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 17 of 29

Serial Interface Specifications

Timing Specifications

SDATA

STD2(Upper data)

STD1(Lower data)

address(address)

SCK

CS

D9

D8

D11

D10

D13

D12

D15

D14

D1

D0

D3

D2

D5

D4

D7

D6

D0

D2

D1

D4

D3

D6

D5

D7

Latches SDATA

at SCK rising edge

Data is determined

at CS rising edge

Figure 8 Serial Interface Timing Specifications

Item

Min

Max

—

5 MHz

50 ns

—

50 ns

—

50 ns

—

Notes: 1. 3 byte continuous communications.

2. Input SCK with 24 clock when CS is Low.

3. It becomes invalid when data communications are stopped on the way.

4. Data becomes a default with hardware reset.

5. Input more than double frequency of SCK to the CLK_in when transfer

the serial data.

The Kind of Data

Data address has 256 type. H’00 to H’FF

H’00

:

:

H’EF

Data at timing generator part

H’F0

:

:

H’FF

Data at CDS part

Address map of each data referred to other sheet.

Details of timing generator refer to the timing chart on the other sheet together with this specification.

This specification only explains about the data of CDS part.