M16C30MC datasheet(67/166 Pages) RENESAS

67 / 166 page

Mitsubishi microcomputers

M16C / 30L Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

This microcomputer has one DMAC (direct memory access controller) channel that allow data to be sent to

memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a

higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this

account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-

bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram

of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers

used by the DMAC.

Figure 1.13.1. Block diagram of DMAC

Data bus low-order bits

DMA latch high-order bits

DMA latch low-order bits

Data bus high-order bits

Address bus

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

(addresses 002916, 002816)

(addresses 002616 to 002416)

Note: Pointer is incremented by a DMA request.

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20) (Note)

(addresses 002216 to 002016)

Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer

request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the

interrupt priority level. The DMA transfer doesn't affect any interrupts either.

If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request

signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA

transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the

number of transfers. For details, see the description of the DMA request bit.

M16C30MC 数据表(PDF) 67 Page - Renesas Technology Corp