MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

20

Fig. 13 Operation of UART serial I/O function

The serial I/O control register consists of eight control bits for the

serial I/O function.

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer. One bit in this register (bit 4) is

The read-only serial I/O1 status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer, and

the receive buffer full flag is set. A write to the serial I/O status reg-

ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-

spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of

the Serial I/O Control Register) also clears all the status flags, in-

cluding the error flags.

All bits of the serial I/O1 status register are initialized to “0” at re-

set, but if the transmit enable bit (bit 4) of the serial I/O control reg-

ister has been set to “1”, the transmit shift completion flag (bit 2)

and the transmit buffer empty flag (bit 0) become “1”.

Transmit buffer/Receive buffer register (TB/

The transmit buffer and the receive buffer are located at the same

address. The transmit buffer is write-only and the receive buffer is

read-only. If a character bit length is 7 bits, the MSB of data stored

in the receive buffer is “0”.

The baud rate generator determines the baud rate for serial trans-

fer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate genera-

tor.

TSC=0

TBE=1

RBF=0

TBE=0

TBE=0

RBF=1

RBF=1

ST

SP

ST

SP

TBE=1

TSC=1

ST

SP

ST

SP

Transmit or receive clock

Transmit buffer write

signal

Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).

2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt

source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes "1".

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

V

V

Receive buffer read

signal