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7516 数据表(PDF) 21 Page - Renesas Technology Corp |
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7516 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 90 page  Rev.1.01 Jul 01, 2003 page 21 of 89 7516 Group Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 Q Q “1” “0” P27/CNTR0/SRDY1 Q Q P40/CNTR1 “0” “1” R R “1” “0” “0” “1” T T Prescaler X latch (8) Prescaler X (8) Timer X latch (8) Timer X (8) To timer X interrupt request bit Toggle flip-flop Timer X count stop bit Pulse width measurement mode Event counter mode To CNTR0 interrupt request bit Pulse output mode Port P27 latch Port P27 direction register CNTR0 active edge selection bit Timer X latch write pulse Pulse output mode Timer mode Pulse output mode Prescaler Y latch (8) Prescaler Y (8) Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit Toggle flip-flop Timer Y count stop bit To CNTR1 interrupt request bit Pulse output mode Port P40 latch Port P40 direction register CNTR1 active edge selection bit Timer Y latch write pulse Pulse output mode Timer mode Pulse output mode Data bus Data bus Prescaler 12 latch (8) Prescaler 12 (8) Timer 1 latch (8) Timer 1 (8) Data bus Timer 2 latch (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit CNTR0 active edge selection bit CNTR1 active edge selection bit Pulse width measure- ment mode Event counter mode f(XCIN) Timer 12 count source selection bit f(XIN)/16 f(XIN)/2 Timer Y count source selection bit f(XIN)/16 f(XIN)/2 Timer X count source selection bit f(XIN)/16 (f(XCIN)/16 at low-speed mode) (f(XCIN)/2 at low-speed mode) (f(XCIN)/16 at low-speed mode) (f(XCIN)/2 at low-speed mode) (f(XCIN)/16 at low-speed mode) |
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