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7546 数据表(PDF) 29 Page - Renesas Technology Corp |
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7546 数据表(HTML) 29 Page - Renesas Technology Corp |
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29 / 95 page  Rev.1.21 Nov 15, 2006 page 29 of 93 REJ03B0160-0121 7546 Group Fig. 25 Block diagram of timer 1 and timer X Q Q P14/CNTR0 R T 1/16 1/2 Timer X interrupt request bit Toggle flip-flop Timer X count stop bit Pulse width measurement mode Event counter mode CNTR0 interrupt request bit Pulse output mode Port P14 latch Port P14 direction register CNTR0 active edge switch bit Timer mode Pulse output mode CNTR0 active edge switch bit Timer X count source selection bits 1/1 P03/TXOUT Prescaler X latch (8) Prescaler X (8) Timer X latch (8) Timer X (8) Data bus “0” “1” “0” “1” Writing to timer X latch Pulse output mode P03/TXOUT output valid Port P03 latch Port P03 direction register Prescaler 1 latch (8) Prescaler 1 (8) Timer 1 latch (8) Timer 1 (8) 1/16 Data bus Timer 1 interrupt request Frequency divider XIN On-chip oscillator “00” “01” “11” “0” “10” Clock division ratio selection bits CPU mode register |
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