STU2071

4B3T U INTERFACE CIRCUIT

PRELIMINARY DATA

4B3T TWO-WIRE U INTERFACE CIRCUIT

FOR LT AND NT APPLICATION

120 kbaud LINE SYMBOL RATE (120 SYM-

BOLS PER FRAME)

SCRAMBLER

AND

DESCRAMBLER

AC-

CORDING TO CCITT REC V.29

BARKER CODE (11 SYMBOLS) SYNCHRO-

NIZATION WORD

UNSCRAMBLED 1 KBIT/S HOUSEKEEPING

CHANNEL

ADAPTIVE

ECHO

CANCELLATION WITH

TRANSVERSAL FILTERING

ADAPTIVE DECISION FEEDBACK EQUALI-

ZATION

AUTOMATIC GAIN CONTROL

PDM AD CONVERTER

AUTOMATIC ACTIVATION AND DEACTIVA-

TION WITH POLARITY ADAPTION

AUTOMATIC CODE VIOLATION DETECTION

POWER FEED UNIT CONTROL

ADVANCED CL3 1.5

µm CMOS PROCESS

28 PIN DUAL-IN-LINE PLASTIC PACKAGE

V* DIGITAL INTERFACE

SYSTEM OVERVIEW

STU2071 (UIC) provides two transparent 64 kbit/s

B channels, a transparent 16 kbit/s D channel, a

transparent 1 kbit/s service channel and a 1 kbit/s

maintenance channel for loop and error mes-

sages on subscriber lines.

UIC enables full duplex continuous data transmis-

sion via the standard twisted pair telephone ca-

ble. Adaptive Echo cancellation is used to restore

the received data. An equalizer, done with an

adaptive filter, restores the data which are dis-

torted by the transmission line.

The coefficient of the equalizer and echo cancel-

ler are conserved during a power down. An all

digital PLL performs both bit and frame synchroni-

zation.

The analog front end consists of receive path RX

and transmit path TX, providing a full duplex ana-

log interfacing to the twisted pair telephone cable.

Before data are converted to analog signals, they

pass through a digital filter (TX-filter) to reduce

the high frequency components. After D/A con-

version the signal is amplified and sent to the hy-

brid.

The received signal is converted back to digital

data and passed through the RX matching filter to

restore the line signal. The A/D convertor is a

second order sigma/delta modulator which oper-

ates with a clock of 15.36 MHz. After timing re-

covery, achieved by a digital PLL, the received

signal is equalized, in an adaptive digital filter, to

correct for the frequency and group delay distor-

tion of the line.

Power supply status can be read via PFOFF. The

UIC can disable its power supply (DISS), and two

relay drivers outputs are provided (accessible via

B2*) to control the power feed unit (RD1,RD2).

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

September 1994

DIP28

ORDERING NUMBER: STU2071B1

PLCC28

ORDERING NUMBER: STU2071FN

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