STV0056 datasheet(4/26 Pages) STMICROELECTRONICS

4 / 26 page

A 12V

Double bonded main power pin for the audio/FM

section of the chip. The two bond connections are

to the ESD and to power the circuit and on chip

regulators/references.

A GND L

This ground pin is double bonded :

1) to channel LEFT : RF section & VCO,

2) to both AGC amplifiers, channel LEFT and

RIGHT audio filter section.

A GND R

This ground pin is double bonded :

1) to the volume control, noise reduction system,

ESD + Mux + VREF

2) to channel right : RF section & VCO

BASEBAND AUDIO PROCESSING

PK OUT L, PK OUT R, PK OUT

The noise reduction control loop peak detector

output requires a capacitor to ground from this pin,

and a resistor to VREF pin to give some accurate

decay time constant. An on chip 5k

Ω ±25 % resistor

and external capacitor give the attack time.

PK IN L, PK IN R or PK IN

Each of these pins is an input to a control loop peak

detector and is connected to the output of the

offchip control loop band pass filter.

LEVEL L, LEVEL R

Respectively the audio left and right signals of the

FM demodulators are output to level L and level R

pins through an input follower buffer. The off-chip

filters driven by these pins must include AC cou-

pling to the next stage (PK IN L and PK IN R pins

respectively).

FC L, FC R

The variable bandwidth transconductance ampli-

fier has a current output which is variable depend-

ing on the input signal amplitude as defined by the

control loop of the noise reduction. The output

current is then dumped into an off-chip capacitor

which together with the accurate current reference

define the min/max rolloff frequencies. Aresistor in

series with a capacitor is connected to ground from

these two pins.

J17 L, J17 R

The external J17 de-emphasis networks for chan-

nels left and right. The amplifier for this filter is

voltage input, current output. Output with

±500mV

input will be

±55µA.

To perform J17 de-emphasis with the STV0042, an

external circuit is required.

U75 L, U75 R

External deemphasis networks for channels left

and right. For each channel a capacitor and resistor

in parallel of 75

µs time constant are connected

between here and VREF to provide 75

µs de-empha-

sis. Internally selectable is an internal resistor that

can be programmed to be added in parallel thereby

converting the network to approx 50

µs de-empha-

sis (see control block map). The value of the inter-

nal resistors is 54k

Ω ±30 %. The amplifier for this

filter is voltage input, current output ; with

±500mV

input the output will be

±55µA.

VOL L, VOL R

The main audio output from the volume control

amplifier the signal to get output signals as high as

2VRMS (+12dB) on a DC bias of 4.8V. Control is

from +12dB to -26.75dB plus Mute with 1.25dB

steps. This amplifier has short circuit protection and

is intended to drive a SCART connector directly via

AC coupling and meets the standard SCART drive

requirements. These outputs feature high imped-

ance mode for parallel connection.

S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R

These audio outputs are sourced directly from the

audio MUX, and as a result do not include any

volume control function. They will output a 1VRMS

signal biased at 4.8V. They are short circuit pro-

tected. These outpu ts feature high impedance

mode for parallel connection and meet SCART

drive requirement.

S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R

These pins allow auxiliary audio signals to be con-

nected to the audio processor and hence makes

use of the on-chip volume control. For additional

details please refer to the audio switching table.

PIN DESCRIPTION (continued)

STV0056A

4/26

STV0056 数据表(PDF) 4 Page - STMicroelectronics

STV0056 数据表(HTML) 4 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表下载