CLOCK OUT

S IGNAL

DIGITAL

S IGNAL

ANALO G

S IGNAL

t

APER

t

PD

t

V

t

CL

N

N+1

N+2

Da ta

for N

Da ta

for N+1

Da ta

for N+2

t

S KEW

Note : This diagram shows a delay of one clock cycle. Additionnal integer multiple delay periods are acceptable. Output data must be valid on

the rising edge of the clock out signal.

Figure 1 : Timing Diagram

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

CLOCK OUTPUT

High Ouput Voltage

2.4

V

Low Output Voltage

0

0.4

V

High Output Current

-4

mA

Low Output Current

4

mA

Clock Duty Cycle

40

60

%

Clock Period

24

ns

REFERENCE LADDER

Top Voltage

V

Bottom Voltage

V

DC Bias Restoration Error

Open input digital output

should be

32/64

011111

33/64

100000

Input Impedance

90

Ω

CROSSTALK

Isolation A/B

37

dB

DC ACCURACY

Integral non Lin.

-0.5

+0.5

LSB

Diff. Non Lin.

-0.5

+0.5

LSB

Effective Number of Bit

5

bits

SNR

33

dB

THD

THD First 5 Harmony

33

dB

Integral non Lin.

-1

+1

LSB

A/D Amplifier Response Mismatching

0.2

dB

STV0190

5/7