STV2001 datasheet(24/46 Pages) STMICROELECTRONICS

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STV2001

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14 - OPERATING DESCRIPTION

SCANNING PART

14.1 - GENERAL CONSIDERATIONS

14.1.1 - Power Supply

Typical power supply voltages are 10.5 V for the

Deflection and Preamplifier sections (SAVCC,

VAVCC and PVCC) and 5.0 V for the logic section

(Vdd). Optimum operation is obtained between 9.5

and 11.5 for VCC, and between 4.5 and 5.5 V for

VDD.

VCC is monitored during the transient phase when

switched either on or off, to avoid erratic operation

of the circuit. If VCC is inferior to 5.0 V typ., the cir-

cuit outputs are inhibited. Similarly, before VDD

reaches 4 V, all the I2C registers are reset to their

default value (see I2C Control Table).

The circuit is internally supplied by several voltage

references (typ. value: 8 V) to ensure a good pow-

er supply rejection. Two of these voltage referenc-

es are externally accessible respectively for the

vertical and horizontal parts. They can be used to

bias external circuitry if ILOAD is inferior to 5 mA.

To minimize the noise and consequently the "jitter"

on vertical and horizontal output signals, the refer-

ence voltages must be filtered by external capaci-

tors connected to the ground.

To further improve the jitter on both vertical and

horizontal sections, FCAP and FILTER pins are

used to filter the internal 5V regulator with external

decoupling capacitors.

14.1.2 - I2C Control

STV2001 belongs to the I2C-controlled device

family. Each adjustment can be made via the I2C

Interface, instead of being controlled by DC voltag-

es on dedicated control pins. The I2C bus is a se-

rial bus with a clock and a data input. General

function and bus protocol are specified in the

Philips-bus data sheets. The interface (Data and

Clock) is TTL-compatible. Spikes up to 50 ns are

filtered by an integrator and the maximum clock

speed is limited to 100 kHz.

The data line (SDA) can be used bidirectionally. In

read mode, the IC sends reply information (1 byte)

to the micro-processor.

The bus protocol prescribes a full-byte transmis-

sion in all cases. The first byte after the start con-

dition is used to transmit the IC address (hexa 8C

for write, 8D for read).

All bytes are sent MSB bit first and the write data

transfer is closed by a stop.

14.1.3 - Write Mode

In write mode, the second byte contains the sub-

address of the selected function to adjust (or con-

trols to effect) and the third byte the corresponding

data byte. More than one data byte can be sent to

the IC. If after the third byte no stop or start condi-

tion is detected, the circuit automatically incre-

ments the momentary subaddress in the subad-

dress counter (auto-increment mode) by one.

Thus it is possible to immediately transmit the fol-

lowing data bytes without sending the IC address

or subaddress. This can be useful for reinitializing

all the controls very quickly (flash manner). This

procedure is ended with a stop condition.

There are 22 adjustment capabilities for the circuit:

3 for the horizontal part, 3 for the vertical, 3 for the

E/W correction, 2 for the dynamic horizontal phase

control, 5 for the preamplifier, 4 for the corners, 2

for EHT compensation and 1 for the blanking DC.

14 bits are also dedicated to several controls (ON/

OFF).

14.1.4 - Read Mode

In the read mode the second byte transmits the re-

ply information. The reply byte contains the hori-

zontal and vertical lock/unlock status, the XRAY

activation status. A stop condition always stops all

the activities of the bus decoder and switches both

the data and clock line (SDA and SCL) to high im-

pedance. See I2C subaddress and control tables.

14.1.5 - Sync Processor

The internal sync processor allows the device to

receive separate horizontal & vertical TTL-com-

patible sync signals.

14.1.6 - IC Status

The IC informs the MCU about both the 1st hori-

zontal PLL (locked or not) and the XRAY protec-

tion (activated or not). The XRAY internal latch is

reset either directly via the I2C interface or by de-

creasing the VCC supply.

14.1.7 - Sync Inputs

Both HIN and VIN inputs are TTL compatible trig-

gers with hysterisis to avoid erratic detection. Both

inputs include a pull-up resistor connected to VDD.

Synchro pulses must be positive.

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