| 数据搜索系统,热门电子元器件搜索 |
|
STV3012 数据表(PDF) 4 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STV3012 数据表(HTML) 4 Page - STMicroelectronics |
|
4 / 8 page ![]() The information is defined by the first edge of the modulated pulses. During mode A, the data word starts with the four bits for defining the sub-system address S3, S2, S1 and S0, followed by the toggle bit T0, and seven bits G, F, E, D, C, B and A, which are defined by the selected key. During mode B, the data word starts with the Toggle bits T1 and T0, followed by three bits for defining the sub-system address S2, S1 and S0, and six bits F, E, D, C, B and A which are defined by the selected key. The toggle bits function as an indication for the decoder that the next instruction has to be consid- ered as a new command. The REMO output is protected against "lock-up", i.e. the length of an output pulse is limited to < 1msec, even if the oscillator stops during an output pulse. This avoids the rapid discharge of the battery that would otherwise be caused by the continuous activation of the LED. Table 1 : Key Codes Matrix Drive Matrix Sense Code Matrix Position G** F E DCBA DRV0N DRV1N DRV2N DRV3N DRV4N DRV5N DRV6N VSS SEN0N SEN0N SEN0N SEN0N SEN0N SEN0N SEN0N SEN0N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 DRV0N to VSS SEN1N 0 0 0 1 * 8 to 15 DRV0N to VSS SEN2N 0 0 1 0 * 16 to 23 DRV0N to VSS SEN3N 0 0 1 1 * 24 to 31 DRV0N to VSS SEN4N 0 1 0 0 * 32 to 39 DRV0N to VSS SEN5N 0 1 0 1 * 40 to 47 DRV0N to VSS SEN6N 0 1 1 0 * 48 to 55 DRV0N to VSS SEN5N and SEN6N 0 1 1 1 * 56 to 63 * The C, B and A codes are identical to SEN0N as given above. ** Bit position G only available in mode A. Table 2 : Transmission Mode and Sub-system Address Selection Mode Sub-system Address Driver DRVnN for n = M O D E A # S3 S2 S1 S0 0123456 0 000 0 1 0 0 1 0 XXXXX O 2 0 1 1 0 XXXX O 3 000 1 X X X O 4 010 1 X X O 5 001 1 X O 6 011 1 O M O D E B 01 1 1 O 10 0 0 O O 20 0 1 X O O 30 1 0 X X O O 4 0 1 1 XXX O O 5 1 0 0 XXXX O O 6 1 0 1 XXXXX O O O = connected to ADRM blank = not connected to ADRM X = don’t care The sub-system address and the transmission mode are defined by connecting the ADRM input to one or more driver outputs (DRV0N to DRV6N) of the key matrix. If more than one driver is connected to ADRM, they must be decoupled by diodes. STV3012 4/8 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |