STV5347 datasheet(9/22 Pages) STMICROELECTRONICS

9 / 22 page

FUNCTIONAL DESCRIPTION (continued)

III - VPS DATA (see Table 2)

VPS data are stored in row 25 chapter 5 as shown

in Table 2 when VPS enable bit (D4 of R8 register)

is set. VPS data bits are decoded and stored in a

received area with biphaseerror bit. 8/30/2data are

stored as received (without hamming decoding) in

Row 23 chapter5 according to Table 2. 8/30 packet

and VPS data decoding is the responsibility of the

control software. The decoder simply stores trans-

mitted data.

IV - I

2C Bus Register Map (see Table 3)

Registers R0 to R10 are write only whilst R11A is

a read/write and R11B is read only.

The automatic succession on a byte by byte basis

is indicated by the arrows in Table 3.

In the normal operating mode TB should be set to

logic level 0.

After power-up the contents of the registers are as

follows : all bits in registers R0 to R11A are cleared

to zero with the exception of bits D0 and D1 in

registers R5 and R6 which are set to logical one.

After power-up all the memory bytes are preset to

hexadecimalvalue 20H (space) with the exception

of the byte corresponding to row 0 of column 7 of

chapter 0 which is set to the value corresponding

to “alpha white” hexadecimal value 07H.

In 4 pages mode, R1D4 (ghost row enable) is set

to ’0’. In this mode, the X/24, X/26, X/27, X/28

packets of the selected pages, and the 8/30 pack-

ets, are not stored.

In 2 pages mode, R1D4 (ghost row enable) is set

’1’. In this mode two displayable pages can be

stored in chapter 0 and 1, and the ghost rows of the

selected pages, and the 8/30 packets, are stored

in chapter 4 and 5.

Column

0123456

789

8/30/2 (Row 23)

Initial Page

b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25

VPS (Row 25)

Received Page Information

B11

B12

B13

B14

B15

Column

8/30/2 (Row 23)

Status Display

VPS (Row 25)

Table 2 : PDC Data Storage in Chapter 5

X24

POSITION

FREE

RUNNING

PLL

(1)

DISABLE

ROLLING

HEADER

(1)

EVEN

OFF

(1)

SEL 11B

Mode 0

(1)

7 + P/

8 BIT

ACQ.

ON/OFF

GHOST

ROW

ENABLE

DEW/

FULL

FIELD

TCS

Mode 1

(1)

BANK

SELECT

(2)

ACQ.

CCT

START

COLUMN

SC2

START

COLUMN

SC1

START

COLUMN

SC0

Page request address

(1)

PRD4

PRD3

PRD2

PRD1

PRD0

Page request data

(1)

(2)

Display chapter

BKGND

OUT

BKGND

COR

OUT

COR

TEXT

OUT

TEXT

PON

OUT

PON

Display control (normal)

BKGND

OUT

BKGND

COR

OUT

COR

TEXT

OUT

TEXT

PON

OUT

PON

Display control

(newsflash / subtitle)

STATUS

ROW

BTM/TOP

CURSOR

ON/OFF

CONCEAL/

REVEAL

TOP/

BOTTOM

SINGLE/

DOUBLE

HEIGHT

BOX ON

1-23

BOX ON

Display mode

(1)

VPS

ENABLE

CLEAR

MEM.

(2)

Active chapter

(1)

Active row

(1)

R10

Active column

(R/W)

R11A

Active data

60Hz

DATA

QUAL

VCS

QUAL

R11B

Status

↵

(1) Reserved register bits : must be set to 0

(2) Inactive

↵

Table 3 : Register Specification

STV5347 - STV5347/H - STV5347/T

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