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STV7610 数据表(PDF) 13 Page - STMicroelectronics

部件名 STV7610
功能描述  PLASMA DISPLAY PANEL DATA DRIVER
PDF  17 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV7610 数据表(HTML) 13 Page - STMicroelectronics

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STV7610A
13/17
AC TIMINGS REQUIREMENTS
(VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR,tF) = 10 ns)
AC TIMINGS CHARACTERISTICS
(VCC =5 V, VPP =90 V, VSPP =0 V, VSSLOG =0 V, VSSSUB =0 V, Tamb =25°C)
(VIL(Max.) = 0.2 Vcc, VIH(Min.) = 0.8 VCC,VOH = 4.0V, VOL = 0.4 V, unless otherwise specified)
Note 6 One output among 96, loading capacitor CL = 50pF, other outputs at low level.
Symbol
Parameter
Min.
Typ.
Max.
Unit
tWHCLK
Duration of clock (CLK) pulse at high level
15
-
-
ns
tWLCLK
Duration of clock (CLK) pulse at low level
15
-
-
ns
tSDAT
Set-up Time of data input before clock (low to high) transition
10
-
-
ns
tHDAT
Hold Time of data input after clock (low to high) transition
10
-
-
ns
tSFR
Forward/
(FOR/
) Set-up Time before clock (low to
high) transition
100
tDSTB
Minimum Delay to latch
after clock (low to high) transition
10
-
-
ns
tSSTB
Minimum Delay to latch
before clock (low to high) transition
10
-
-
ns
tSTB
Latch
Low Level Pulse Duration
20
-
-
ns
tBLK
Blanking
Pulse Duration
500
-
-
ns
tPOL
Polarity
Pulse Duration
500
-
-
ns
Symbol
Parameter
Min.
Typ. Max. Unit
tCLK
Data clock Period
50
-
-
ns
tRDAT
Logical Data Output Rise Time (CL=10pF)
-
12
20
ns
tFDAT
Logical Data Output Fall Time (CL=10pF)
-
11
20
ns
tPHL1
tPLH1
Delay of logic data output (high to low transition) after clock (CLK) transition
Delay of logic data output (low to high transition) after clock (CLK) transition
-
-
30
30
50
50
ns
ns
tPHL2
tPLH2
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
-
-
135
80
180
180
ns
ns
tPHL3
tPLH3
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
-
-
115
70
165
165
ns
ns
tPHL4
tPLH4
Delay of power output change (high to low transition) to Blank or Polarity
(
,
) transition
Delay of power output change (low to high transition) to Blank or Polarity
(
,
) transition
-
-
100
55
160
160
ns
ns
tROUT
Power Output Rise Time ( Note 6)
-
50
150
ns
tFOUT
Power Output Fall Time ( Note 6)
-
80
200
ns
reverse
REV
ST B
()
ST B
()
ST B
()
BLK
()
PO L
()
BLK PO L
BLK PO L
3



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