STV7617, STV7617D, STV7617U

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BLOCK DIAGRAM

CIRCUIT DESCRIPTION

The STV7617 contains all the logic and the power

circuits necessary to drive rows of a Plasma Dis-

play Panel (PDP). Data is shifted at each low to

high transition of the (CLK) shift clock. After 64 or

65 shifts (depending on SEL) the first bit presented

at (SIN) is available at the serial output (SOUT).

This output can be used to cascade several driv-

ers to perform any vertical resolution. CLK, STB,

SIN and SOUT inputs are Smith trigger inputs.

BLK and HIZ logical inputs are internally pulled to

level ”1”. The maximum frequency of the shift

clock is 8 MHz.

Shift register outputs (P1, ... P65) are transferred

from the shift register into the latch stage when the

latch input (STB) is at low level.

Table 1 : Output State Configuration

Sustain current must not be sunk in the power out-

puts to VPP when the power supply is applied and

the logical reference ground of the application.

Table 2 : Shift Register Truth Table

Table 3 : Power Output Configuration

P1

P65

LATCH

Q1

Q65

Q2

Q64

S65

S1

V

SSP

V

PP

V

CC

V

SSL OG

SOUT (SIN)

SIN (SOUT)

STB

BLK

HIZ

OUT1

OUT65

STV7617

CLK

V

PP

V

SSP

V

PP

V

SSP

V

CC

V

CC

V

SSS UB

OUT64

65-BIT SHIFT REGISTER

SEL

F/R

SWITCH

STB

BLK

HIZ

Outp ut State

*

L

L

High impedance

LL

H

Inverted copy of input

data

H

L

H

Data latched

*

H

L

Low level

*

H

H

High Level

F/R

CLK

SIN

SOUT

Comments

H

Rise

In

Out

Forward Shift

H

L or H

In

Out

Steady

L

Rise

Out

In

Reverse Shift

L

L or H

Out

In

Steady

SEL

F/R

Number of

Outpu ts

Comments

LL

64

Out 1 is in Hi-Z mode (out-

puts 65 to 2 powered)

LH

64

Out 65 is in Hi-Z mode (out-

puts 1 to 64 powered)

H

L

65

Out 65 to Out 1 powered

H

H

65

Out 1 to Out 65 powered

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