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M35054 数据表(PDF) 21 Page - Renesas Technology Corp |
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M35054 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 41 page ![]() M35054-XXXFP/M35055-XXXFP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MITSUBISHI MICROCOMPUTERS 20 DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by then serial input function. Owing to automatic address increment, not necessary to enter ad- dresses for the second and subsequent data. In automatically, the next of address F816 is assigned to address 0016. Fig. 9 shows an example of data setting by the serial input function (M35054-XXXFP), Fig. 10 shows an example of data setting by the serial input function (M35055-XXXFP). Fig. 9 Example of data setting by the serial input function (M35054-XXXFP) Address/Data Data(F116) Data(F216) Data(F316) Data(F416) Data(F516) Data(F616) Data(F716) Data(F816) Data(F016) Spplemental explanation Data contewts NO. 1 Address(F816) Address setting Data(F816) Data(0016) 2 3 4 241 Data(0116) Data(EF16) Display OFF Display RAM address 0016 to EF16 setting Display ON Data(EE16) 242 243 244 245 246 247 248 249 250 251 Register address F016 to F716 setting DA DA DA FE D 00 00 0 00 0 00 0 00 0 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 1 00 0 00 DA DA DA DA DA DA DA DA DA DA DA DA DA C B A 98 7 6 54 32 1 0 00 0 00 0 0 0 11111 0 0 0 0 0 00000 0 0 0 C6 C5 C4 C3 C2 C0 C1 B BLINK GR REV C6 C5 C4 C3 C2 C0 C1 BLINK REV C6 C5 C4 C3 C2 C0 C1 BLINK REV C6 C5 C4 C3 C2 C0 C1 BLINK REV HP HP HP HP HP VSZ VSZ VSZ VSZ HSZ SPACE DSP DSP DSP DSP DSP DSP DSP EQP PALH MPAL /NON N/P TEST TEST TEST LBLACK LIN BLKHF BB BG BR LEVEL PHASE LEVEL RAM DSPON STOP STOP SCOR 00 HP HSZ DSP BLINK EX HP HSZ DSP BLINK BLK PTC HP HSZ DSP BLINK BLK CURS 0 PTC 1 PTD 0 PTD 1 0 1 2 3 4 5 6 7 VP VP VP VP VP VP VP VP 0 1 2 3 4 5 6 7 10 11 20 21 10 11 20 21 0 0 0 1 2 3 4 5 6 7 8 9 0 0 1 2 0 1 2 0 PHASE PHASE 0 1 2 0 1 IN 1 ERS 24/32 1 1 CURS CURS CURS CURS CURS CURS CURS 0 1 2 3 4 5 6 7 INT 01 0 00 00 CBLINK CL 17/18 RGBON 0 0 0 1 0 0 0 0 0 0 BG R BG R BG R 00 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 |
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