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SH7211 数据表(PDF) 86 Page - Renesas Technology Corp |
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SH7211 数据表(HTML) 86 Page - Renesas Technology Corp |
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86 / 1228 page ![]() Section 4 Clock Pulse Generator (CPG) Rev. 2.00 May. 08, 2008 Page 62 of 1200 REJ09B0344-0200 [Legend] Frequency control register MTU2S clock frequency control register AD clock frequency control register Standby control register Standby control register 2 Standby control register 3 Standby control register 4 FRQCR: MCLKCR: ACLKCR: STBCR: STBCR2: STBCR3: STBCR4: FRQCR MCLKCR ACLKCR STBCR STBCR2 STBCR3 STBCR4 Bus interface MD_CLK2 MD_CLK0 CPG control unit Clock frequency control circuit Standby control circuit CK EXTAL XTAL PLL circuit 1 ( ×1, 2, 4) PLL circuit 2 ( ×4) Divider 1 MTU2S clock (M φ, Max. 80 MHz) AD clock (A φ, Max. 40 MHz) Internal clock (I φ, Max. 160 MHz) Peripheral clock (P φ, Max. 40 MHz) Bus clock (B φ = CK, Max. 40 MHz) Crystal oscillator On-chip oscillator HPB bus ×1 ×1/2 ×1/4 ×1/8 Figure 4.1 Block Diagram of Clock Pulse Generator |
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