R4F2117 datasheet(21/968 Pages) RENESAS

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Rev. 2.00 Feb. 20, 2008 Page xxi of xxiv

18.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 588

18.5.3 Module Stop Mode Setting ................................................................................... 588

18.5.4 Medium-Speed Mode............................................................................................ 588

18.5.5 Transmit Completion Flag (KBTE) ...................................................................... 588

Section 19 LPC Interface (LPC) ........................................................................589

19.1

Features .............................................................................................................................. 589

19.2

Input/Output Pins ............................................................................................................... 592

19.3

Register Descriptions ......................................................................................................... 593

19.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 595

19.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 601

19.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 604

19.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 605

19.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L)................ 606

19.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)................ 607

19.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 609

19.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 611

19.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 612

19.3.10 Output Data Registers 1 to 4 (ODR1 to ODR4).................................................... 612

19.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) ..................................... 613

19.3.12 Status Registers 1 to 4 (STR1 to STR4)................................................................ 613

19.3.13 SERIRQ Control Register 0 (SIRQCR0).............................................................. 620

19.3.14 SERIRQ Control Register 1 (SIRQCR1).............................................................. 624

19.3.15 SERIRQ Control Register 2 (SIRQCR2).............................................................. 628

19.3.16 SERIRQ Control Register 3 (SIRQCR3).............................................................. 631

19.3.17 SERIRQ Control Register 4 (SIRQCR4).............................................................. 632

19.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 633

19.3.19 Host Interface Select Register (HISEL)................................................................ 634

19.4

Operation ........................................................................................................................... 635

19.4.1 LPC interface Activation ...................................................................................... 635

19.4.2 LPC I/O Cycles ..................................................................................................... 635

19.4.3 Gate A20 ............................................................................................................... 638

19.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 641

19.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ)...................................... 645

19.4.6 LPC Interface Clock Start Request ....................................................................... 647

19.4.7 SCIF Control from LPC Interface......................................................................... 647

19.5

Interrupt Sources................................................................................................................ 648

19.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ..................................................... 648

19.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,

HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 648

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