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M16C/29 数据表(PDF) 225 Page - Renesas Technology Corp |
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M16C/29 数据表(HTML) 225 Page - Renesas Technology Corp |
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225 / 499 page  14. Serial I/O p u o r G 9 2 / C 6 1 M page 201 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 14.23 Transfer to U2RB Register and Interrupt Timing (4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1 (3) When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0 SDA2 SCL2 Receive interrupt (DMA request) Transmit interrupt SDA2 SCL2 The above timing applies to the following setting : • The CKDIR bit in the U2MR register is set to 1 (slave) (1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (No clock delay) D6 D5 D4 D3 D2 D1 D8 (ACK or NACK) D7 SDA2 SCL2 D0 ACK interrupt (DMA request) or NACK interrupt (2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay) SDA2 SCL2 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 ••• b9 b8 b7 b0 D8 Contents of the U2RB register b15 ••• b9 b8 b7 b0 b15 ••• b9 b8 b7 b0 b15 ••• b9 b8 b7 b0 b15 ••• b9 b8 b7 b0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D7 D0 ACK interrupt (DMA request) or NACK interrupt D8 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Data is transferred to the U2RB register Data is transferred to the U2RB register Data is transferred to the U2RB register Receive interrupt (DMA request) Transmit interrupt Data is transferred to the U2RB register Data is transferred to the U2RB register Contents of the U2RB register Contents in the U2RB register Contents in the U2RB register Contents in the U2RB register |
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