H8SSLASH2240 datasheet(335/818 Pages) RENESAS

335 / 818 page

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 293 of 772

REJ09B0355-0300

Bits 7, 6, 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the

TCNT counter clearing source.

Bit 7

Bit 6

Bit 5

Channel

CCLR2

CCLR1

CCLR0

Description

TCNT clearing disabled

(Initial value)

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous

clearing/synchronous operation*

TCNT clearing disabled

TCNT cleared by TGRC compare match/input

capture*

TCNT cleared by TGRD compare match/input

capture*

TCNT cleared by counter clearing for another

channel performing synchronous

clearing/synchronous operation*

Bit 7

Bit 6

Bit 5

Channel

Reserved*

3 CCLR1

CCLR0

Description

1, 2

TCNT clearing disabled

(Initial value)

TCNT cleared by TGRA compare match/input

capture

TCNT cleared by TGRB compare match/input

capture

TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

3. Bit 7 is reserved in channels 1and 2. It is always read as 0 and cannot be modified.

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