H8SSLASH2240 datasheet(338/818 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 296 of 772

REJ09B0355-0300

9.2.2

Timer Mode Register (TMDR)

—

BFB

R/W

BFA

R/W

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

R/W

Channel 0: TMDR0

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

R/W

Channel 1: TMDR1

Channel 2: TMDR2

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers

are initialized to H'C0 by a reset, and in hardware standby mode.

TCNT operation should be stopped when making TMDR settings.

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer

In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be

modified.

Bit 5

BFB

Description

TGRB operates normally

(Initial value)

TGRB and TGRD used together for buffer operation

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