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H8S/2240 数据表(PDF) 356 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 356 Page - Renesas Technology Corp |
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356 / 818 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 314 of 772 REJ09B0355-0300 9.2.8 Timer Start Register (TSTR) 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 0 CST0 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W Bit Initial value R/W : : : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TSTR is initialized to H'00 by a reset, and in hardware standby mode. TCNT counter operation should be stopped when setting the operating mode in TMDR or the TCNT count clock in TCR. Bits 7 and 3—Reserved: Should always be written with 0. Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn Description 0 TCNTn count operation is stopped (Initial value) 1 TCNTn performs count operation n = 2 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. |
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