H8SSLASH2240 datasheet(423/818 Pages) RENESAS

部件名	H8S/2240

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

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制造商	RENESAS [Renesas Technology Corp]

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Section 10 8-Bit Timers

Rev.3.00 Mar. 26, 2007 Page 381 of 772

REJ09B0355-0300

10.6

Usage Notes

Application programmers should note that the following kinds of contention can occur in the 8-bit

timer.

10.6.1

Setting Module Stop Mode

The TMR is enabled or disabled by setting the module stop control register. In the initial state, the

TMR is disabled. After the module stop mode is canceled, registers can be accessed. For details,

see section 18, Power-Down Modes.

10.6.2

Contention between TCNT Write and Clear

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear

takes priority, so that the counter is cleared and the write is not performed.

Figure 10.10 shows this operation.

Address

TCNT address

Internal write signal

Counter clear signal

TCNT

H'00

TCNT write cycle by CPU

Figure 10.10 Contention between TCNT Write and Clear

H8S/2240 数据表(PDF) 423 Page - Renesas Technology Corp