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H8S/2240 数据表(PDF) 419 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 419 Page - Renesas Technology Corp |
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419 / 818 page  Section 10 8-Bit Timers Rev.3.00 Mar. 26, 2007 Page 377 of 772 REJ09B0355-0300 10.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7 shows the timing of this operation. φ Clear signal External reset input pin TCNT N H'00 N–1 Figure 10.7 Timing of External Reset 10.3.4 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 10.8 shows the timing of this operation. φ OVF Overflow signal TCNT H'FF H'00 Figure 10.8 Timing of OVF Setting |
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