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H8S/2240 数据表(PDF) 418 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 418 Page - Renesas Technology Corp |
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418 / 818 page  Section 10 8-Bit Timers Rev.3.00 Mar. 26, 2007 Page 376 of 772 REJ09B0355-0300 Timer output timing When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 10.5 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 10.5 Timing of Timer Output Timing of Compare Match Clear The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.6 shows the timing of this operation. φ N H'00 Compare match signal TCNT Figure 10.6 Timing of Compare Match Clear |
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