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H8S/2240 数据表(PDF) 417 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 417 Page - Renesas Technology Corp |
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417 / 818 page  Section 10 8-Bit Timers Rev.3.00 Mar. 26, 2007 Page 375 of 772 REJ09B0355-0300 φ External clock input Clock input to TCNT TCNT N–1 N N+1 Figure 10.3 Count Timing for External Clock Input 10.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB) The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 10.4 shows this timing. φ TCNT N N+1 TCOR N Compare match signal CMF Figure 10.4 Timing of CMF Setting |
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