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H8S/2240 数据表(PDF) 442 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 442 Page - Renesas Technology Corp |
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442 / 818 page  Section 11 Watchdog Timer Rev.3.00 Mar. 26, 2007 Page 400 of 772 REJ09B0355-0300 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2245 Group chip. Figure 11.7 shows the timing in this case. φ TCNT H'FF H'00 Overflow signal (internal signal) WOVF WDTOVF signal Internal reset signal 132 states 518 states Figure 11.7 Timing of Setting of WOVF 11.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. |
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