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H8S/2240 数据表(PDF) 443 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 443 Page - Renesas Technology Corp |
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443 / 818 page  Section 11 Watchdog Timer Rev.3.00 Mar. 26, 2007 Page 401 of 772 REJ09B0355-0300 11.5 Usage Notes 11.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation. Address φ Internal write signal TCNT input clock pulse TCNT NM T1 T2 TCNT write cycle Counter write data Figure 11.8 Contention between TCNT Write and Increment 11.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. |
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