H8SSLASH2240 datasheet(455/818 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.3.00 Mar. 26, 2007 Page 413 of 772

REJ09B0355-0300

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the

baud rate generator. The clock source can be selected from

φ, φ/4, φ/16, and φ/64, according to the

setting of bits CKS1 and CKS0.

For the relation between the clock source, the bit rate register setting, and the baud rate, see

section 12.2.8, Bit Rate Register (BRR).

Bit 1

Bit 0

CKS1

CKS0

Description

φ clock

(Initial value)

φ/4 clock

φ/16 clock

φ/64 clock

12.2.6

Serial Control Register (SCR)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

R/W

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output

in asynchronous mode, and interrupt requests, and selection of the serial clock source.

SCR can be read or written to by the CPU at all times.

SCR is initialized to H'00 by a reset, and in standby mode or module stop mode.

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt

(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE

flag in SSR is set to 1.

Bit 7

TIE

Description

Transmit data empty interrupt (TXI) requests disabled*

(Initial value)

Transmit data empty interrupt (TXI) requests enabled

Note:

TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,

then clearing it to 0, or clearing the TIE bit to 0.

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