H8SSLASH2240 datasheet(452/818 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.3.00 Mar. 26, 2007 Page 410 of 772

REJ09B0355-0300

12.2.5

Serial Mode Register (SMR)

R/W

CHR

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

R/W

SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate

generator clock source.

SMR can be read or written to by the CPU at all times.

SMR is initialized to H'00 by a reset, and in standby mode or module stop mode.

Bit 7—Communication Mode (C/

A): Selects asynchronous mode or clocked synchronous mode

as the SCI operating mode.

Bit 7

Description

Asynchronous mode

(Initial value)

Clocked synchronous mode

Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In

clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.

Bit 6

CHR

Description

8-bit data

(Initial value)

7-bit data*

Note:

When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not

possible to choose between LSB-first or MSB-first transfer.

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