H8SSLASH2240 datasheet(449/818 Pages) RENESAS

449 / 818 page

Section 12 Serial Communication Interface (SCI)

Rev.3.00 Mar. 26, 2007 Page 407 of 772

REJ09B0355-0300

12.1.4

The SCI has the internal registers shown in table 12.2. These registers are used to specify

asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control

transmitter/receiver.

Table 12.2

SCI Registers

Channel

Name

Abbreviation

R/W

Initial Value

Address*

Serial mode register 0

SMR 0

R/W

H'00

H'FF78

Bit rate register 0

BRR 0

R/W

H'FF

H'FF79

Serial control register 0

SCR 0

R/W

H'00

H'FF7A

Transmit data register 0

TDR 0

R/W

H'FF

H'FF7B

Serial status register 0

SSR 0

R/(W)*

H'84

H'FF7C

Receive data register 0

RDR 0

H'00

H'FF7D

Smart card mode register 0

SCMR0

R/W

H'F2

H'FF7E

Serial mode register 1

SMR1

R/W

H'00

H'FF80

Bit rate register 1

BRR1

R/W

H'FF

H'FF81

Serial control register 1

SCR1

R/W

H'00

H'FF82

Transmit data register 1

TDR1

R/W

H'FF

H'FF83

Serial status register 1

SSR1

R/(W)*

H'84

H'FF84

Receive data register 1

RDR1

H'00

H'FF85

Smart card mode register 1

SCMR1

R/W

H'F2

H'FF86

Serial mode register 2

SMR2

R/W

H'00

H'FF88

Bit rate register 2

BRR2

R/W

H'FF

H'FF89

Serial control register 2

SCR2

R/W

H'00

H'FF8A

Transmit data register 2

TDR2

R/W

H'FF

H'FF8B

Serial status register 2

SSR2

R/(W)*

H'84

H'FF8C

Receive data register 2

RDR2

H'00

H'FF8D

Smart card mode register 2

SCMR2

R/W

H'F2

H'FF8E

All

Module stop control register

MSTPCR

R/W

H'3FFF

H'FF3C

Notes: 1. Lower 16 bits of the address.

2. Can only be written with 0 for flag clearing.

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