H8SSLASH2240 datasheet(543/818 Pages) RENESAS

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Section 13 Smart Card Interface

Rev.3.00 Mar. 26, 2007 Page 501 of 772

REJ09B0355-0300

• Retransfer operation when SCI is in transmit mode

Figure 13.12 illustrates the retransfer operation when the SCI is in transmit mode.

[6] If an error signal is sent back from the receiving end after transmission of one frame is

completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI

interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next

parity bit is sampled.

[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality

is received.

[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

[9] If an error signal is not sent back from the receiving end, transmission of one frame, including

a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE

bit in SCR is enabled at this time, a TXI interrupt request is generated.

If data transfer by the DTC by means of the TXI source is enabled, the next data can be written

to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is

automatically cleared to 0 if DISEL in DTC is 0 and the transfer counter value is not 0.

D0 D1 D2 D3 D4 D5 D6 D7 Dp DE

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

(DE)

Ds D0 D1 D2 D3 D4

Transfer

frame n+1

Retransferred frame

nth transfer frame

TDRE

TEND

[6]

FER/ERS

Transfer to TSR from TDR

[7]

[9]

[8]

Transfer to TSR from TDR

Transfer to TSR

from TDR

Figure 13.12 Retransfer Operation in SCI Transmit Mode

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