H8SSLASH2240 datasheet(559/818 Pages) RENESAS

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Section 14 A/D Converter

Rev.3.00 Mar. 26, 2007 Page 517 of 772

REJ09B0355-0300

14.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time t

D after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D

conversion timing. Table 14.4 indicates the A/D conversion time.

As indicated in figure 14.5, the A/D conversion time includes t

D and the input sampling time. The

length of t

D varies depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 14.4.

In scan mode, the values given in table 14.4 apply to the first conversion time. In the second and

subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states

when CKS = 1.

(1)

(2)

SPL

CONV

Input sampling

timing

ADF

Address bus

Write signal

Legend:

(1)

: ADCSR write cycle

(2)

: ADCSR address

: A/D conversion start delay

tSPL

: Input sampling time

tCONV : A/D conversion time

Figure 14.5 A/D Conversion Timing

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