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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2240 数据表(PDF) 591 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 591 Page - Renesas Technology Corp |
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591 / 818 page  Section 17 Clock Pulse Generator Rev.3.00 Mar. 26, 2007 Page 549 of 772 REJ09B0355-0300 External Clock The external clock signal should have the same frequency as the system clock ( φ). Table 17.4 and figure 17.6 show the input conditions for the external clock. Table 17.4 External Clock Input Conditions V CC = 2.7 V to 5.5 V V CC = 2.7 V to 5.5 V* V CC = 5.0 V ±10% Item Symbol Min Max Min Max Min Max Unit Test Conditions External clock input pulse width low level t EXL 40 — 30 — 20 — ns Figure 17.6 External clock input pulse width high level t EXH 40 — 30 — 20 — ns External clock rise time t EXr — 10 — 7.5 — 5ns External clock fall time t EXf — 10 — 7.5 — 5ns t CL 0.4 0.6 0.4 0.6 0.4 0.6 t cyc φ ≥ 5 MHz Clock pulse width low level 80 — 80 — 80 — ns φ < 5 MHz Figure 19.4 t CH 0.4 0.6 0.4 0.6 0.4 0.6 t cyc φ ≥ 5 MHz Clock pulse width high level 80 — 80 — 80 — ns φ < 5 MHz Note: * Does not apply to the HD6472246. Table 17.5 and figure 17.6 show the external clock input conditions when the duty adjustment circuit is not used. When the duty adjustment circuit is not used, the φ output waveform depends on the external clock input waveform, and therefore no specifications are provided. |
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