H8SSLASH2240 datasheet(595/818 Pages) RENESAS

595 / 818 page

Section 17 Clock Pulse Generator

Rev.3.00 Mar. 26, 2007 Page 553 of 772

REJ09B0355-0300

17.4

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate the system clock (

φ).

17.5

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate

φ/2, φ/4, φ/8, φ/16, and φ/32.

17.6

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (

φ) or one of the medium-speed

clocks (

φ/2, φ/4, φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of

the SCK2 to SCK0 bits in SCKCR.

17.7

Note on Crystal Resonator

As various characteristics related to the crystal resonator are closely linked to the user's board

design, thorough evaluation is necessary on the user's part, using the resonator connection

examples shown in this section as a guide. As the resonator circuit ratings will depend on the

floating capacitance of the resonator and the mounting circuit, the ratings should be determined in

consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the

maximum rating is not applied to the oscillator pin.

H8S/2240 数据表(PDF) 595 Page - Renesas Technology Corp