H8SSLASH2240 datasheet(749/818 Pages) RENESAS

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Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 707 of 772

REJ09B0355-0300

TCSR—Timer Control/Status Register

H'FFBC (W) H'FFBC (R)

WDT

OVF

R/(W)*1

WT/

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

[Clearing condition]

Cleared by reading TCSR when OVF = 1, then writing 0 to OVF*2

Overflow Flag

Interval timer mode: Sends the CPU an interval timer interrupt request

(WOVI) when TCNT overflows

Watchdog timer mode: Generates the WDTOVF signal when

TCNT overflows

Timer Mode Select

TCNT is initialized to H'00 and halted

TCNT counts

Timer Enable

Clock Select

CKS2 CKS1 CKS0

Clock

Overflow period*

(when

φ = 20 MHz)

φ/2 (initial value)

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

25.6 µs

819.2 µs

1.6 ms

6.6 ms

26.2 ms

104.9 ms

419.4 ms

1.68 s

Notes: The method for writing to TCSR is different from that for general registers to prevent accidental overwriting.

For details see section 11.2.4, Notes on Register Access.

1. Can only be written with 0 for flag clearing.

2. When polling OVF with the interval timer interrupt disabled, read TSCR twice or more while OVF is set to 1.

Note: *

Bit

Initial value

Read/Write

The overflow period is the time from when TCNT

starts counting up from H'00 until overflow occurs.

[Setting condition]

Set when TCNT overflows from H'FF to H'00 in interval timer mode

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