H8SSLASH2240 datasheet(752/818 Pages) RENESAS

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Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 710 of 772

REJ09B0355-0300

TSTR—Timer Start Register

H'FFC0

TPU

—

CST0

R/W

CST2

R/W

CST1

R/W

Counter Start

TCNTn count operation is stopped

TCNTn performs count operation

Note:

Note: n = 2 to 0

If 0 is written to the CST bit during operation with the TIOC pin designated for output, the

counter stops but the TIOC pin output compare output level is retained. If TIOR is written to

when the CST bit is cleared to 0, the pin output level will be changed to the set initial output

value.

Bit

Initial value

Read/Write

TSYR—Timer Synchro Register

H'FFC1

TPU

—

SYNC0

R/W

SYNC2

R/W

SYNC1

R/W

Timer Synchronization

TCNTn operates independently (TCNT presetting/

clearing is unrelated to other channels)

Note: n = 2 to 0

Notes:

To set synchronous operation, the SYNC bits for at least two channels must

be set to 1.

To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing

source must also be set by means of bits CCLR2 to CCLR0 in TCR.

Bit

Initial value

Read/Write

TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing

is possible

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