H8SSLASH2240 datasheet(102/818 Pages) RENESAS

102 / 818 page

Section 2 CPU

Rev.3.00 Mar. 26, 2007 Page 60 of 772

REJ09B0355-0300

(2) Reset Exception Handling

After the

RES pin has gone low and the reset state has been entered, when RES goes high again,

reset exception handling starts. When reset exception handling starts the CPU fetches a start

address (vector) from the exception vector table and starts program execution from that address.

All interrupts, including NMI, are disabled during reset exception handling and after it ends.

(3) Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer

(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU

alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start

address (vector) from the exception vector table and program execution starts from that start

address.

Figure 2.16 shows the stack after exception handling ends.

Note: * Ignored when returning.

CCR

(24 bits)

CCR

CCR*

(16 bits)

Normal mode

Advanced mode

Figure 2.16 Stack Structure after Exception Handling (Examples)

H8S/2240 数据表(PDF) 102 Page - Renesas Technology Corp