H8SSLASH2240 datasheet(104/818 Pages) RENESAS

部件名	H8S/2240

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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104 / 818 page

Section 2 CPU

Rev.3.00 Mar. 26, 2007 Page 62 of 772

REJ09B0355-0300

2.9

Basic Timing

2.9.1

Overview

The H8S/2000 CPU is driven by a system clock, denoted by the symbol

φ. The period from one

rising edge of

φ to the next is referred to as a "state." The memory cycle or bus cycle consists of

one, two, or three states. Different methods are used to access on-chip memory, on-chip

supporting modules, and the external address space.

2.9.2

On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows

the pin states.

Internal address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Bus cycle

Address

Read data

Write data

Read

access

Write

access

Figure 2.17 On-Chip Memory Access Cycle

H8S/2240 数据表(PDF) 104 Page - Renesas Technology Corp