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H8S/2240 数据表(PDF) 185 Page - Renesas Technology Corp

部件名 H8S/2240
功能描述  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2240 数据表(HTML) 185 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 143 of 772
REJ09B0355-0300
6.2.5
Bus Control Register L (BCRL)
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
EAE
1
R/W
4
—
1
(R/W)
3
—
1
(R/W)
0
WAITE
0
R/W
2
ASS
1
R/W
1
—
0
(R/W)
Bit
Initial value
R/W
:
:
:
BCRL is an 8-bit readable/writable register that performs selection of the external bus release state
protocol, selection of the area partition unit and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
Description
0
External bus release is disabled.
BREQ, BACK, and BREQO can be used as I/O ports.
(Initial value)
1
External bus release is enabled.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (
BREQ) in the external bus release state, when an internal bus
master performs an external space access.
Bit 6
BREQOE
Description
0
BREQO output disabled. BREQO can be used as I/O port.
(Initial value)
1
BREQO output enabled.



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