H8SSLASH2240 datasheet(183/818 Pages) RENESAS

183 / 818 page

Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 141 of 772

REJ09B0355-0300

6.2.4

Bus Control Register H (BCRH)

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

—

(R/W)

—

(R/W)

—

(R/W)

Bit

Initial value

R/W

BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle

insertion, and the memory interface for area 0.

BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not

initialized by a manual reset or in software standby mode.

Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted

between bus cycles when successive external read cycles are performed in different areas.

Bit 7

ICIS1

Description

Idle cycle not inserted in case of successive external read cycles in different areas.

Idle cycle inserted in case of successive external read cycles in different areas.

(Initial value)

Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted

between bus cycles when successive external read and external write cycles are performed.

Bit 6

ICIS0

Description

Idle cycle not inserted in case of successive external read and external write cycles.

Idle cycle inserted in case of successive external read and external write cycles.

(Initial value)

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