H8SSLASH2240 datasheet(283/818 Pages) RENESAS

283 / 818 page

Section 8 I/O Ports

Rev.3.00 Mar. 26, 2007 Page 241 of 772

REJ09B0355-0300

Table 8.11

Port A Registers

Name

Abbreviation

R/W

Initial Value*

Address*

Port A data direction register

PADDR

H'0

H'FEB9

Port A data register

PADR

R/W

H'0

H'FF69

Port A register

PORTA

Undefined

H'FF59

Port A MOS pull-up control register

PAPCR

R/W

H'0

H'FF70

Port A open-drain control register

PAODR

R/W

H'0

H'FF77

Notes: 1. Value of bits 3 to 0.

2. Lower 16 bits of the address.

Port A Data Direction Register (PADDR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PA3DDR

PA0DDR

PA2DDR

PA1DDR

Bit

Initial value

R/W

PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port A. Bits 7 to 4 are reserved. PADDR cannot be read; if it is, an undefined value will be

read. PADDR cannot be modified.

This register is a write-only register, and cannot be written by bit manipulation instruction. For

details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.

PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR

is used to select whether the address output pins retain their output state or become high-

impedance when a transition is made to software standby mode.

• Modes 1, 2, 3, and 7

Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing

the bit to 0 makes the pin an input port.

Note:

Modes 2, 3, and 7 cannot be used in the H8S/2240.

• Modes 4 and 5

The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to

PA0DDR.

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