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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663 数据表(PDF) 436 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 436 Page - Renesas Technology Corp |
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436 / 1158 page  Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 384 of 1102 REJ09B0294-0100 (5) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.38 shows an example of single address mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after one cycle of the transfer request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Min. of 3 cycles Min. of 3 cycles DMA single cycle DMA single cycle B φ DREQ Address bus Channel [1] [2] [3] [4] [5] [6] [7] [1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].) Transfer source/ Transfer destination Bus released Bus released Transfer request enable resumed Transfer request enable resumed Transfer source/ Transfer destination Request Request Duration of transfer request disabled Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Duration of transfer request disabled which is extended by NRD Bus released Figure 7.38 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 |
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