H8SXSLASH1663 datasheet(440/1158 Pages) RENESAS

440 / 1158 page

Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 388 of 1102

REJ09B0294-0100

7.7

Relationship among DMAC and Other Bus Masters

7.7.1

CPU Priority Control Function Over DMAC

The CPU priority control function over DMAC can be used according to the CPU priority control

and DMAC.

The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for

each channel.

The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to

CPUP0 is updated according to the exception handling priority.

If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority

over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not

activated. When another channel has priority over or the same as the CPU, a transfer request is

received regardless of the priority between channels and the transfer is activated.

The transfer request masked by the CPU priority control function is suspended. When the transfer

channel is given priority over the CPU by changing priority levels of the CPU or channel, the

transfer request is received and the transfer is resumed. Writing 0 to the DTE bit clears the

suspended transfer request.

When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority.

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