H8SXSLASH1663 datasheet(616/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 564 of 1102

REJ09B0294-0100

Channel Name

Interrupt Source

Interrupt Flag

DTC

Activa-

tion

DMAC

Activa-

tion

TGI4A

TGRA_4 input capture/compare match

TGFA_4

TGI4B

TGRB_4 input capture/compare match

TGFB_4



TCI4V

TCNT_4 overflow

TCFV_4



TCI4U

TCNT_4 underflow

TCFU_4



TGI5A

TGRA_5 input capture/compare match

TGFA_5

TGI5B

TGRB_5 input capture/compare match

TGFB_5



TCI5V

TCNT_5 overflow

TCFV_5



TCI5U

TCNT_5 underflow

TCFU_5



[Legend]

O : Possible

 : Not possible

Note:

This table shows the initial state immediately after a reset. The relative channel priority

levels can be changed by the interrupt controller.

(1) Input Capture/Compare Match Interrupt

An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1

by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is

cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

(2) Overflow Interrupt

An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to

1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing

the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel.

(3) Underflow Interrupt

An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to

1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by

clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4,

and 5.

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