H8SXSLASH1663 datasheet(624/1158 Pages) RENESAS

624 / 1158 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 572 of 1102

REJ09B0294-0100

(4) Status Flag Clearing Timing

After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or

DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag

clearing by the CPU, and figures 10.43 and 10.44 show the timing for status flag clearing by the

DTC or DMAC.

Status flag

Interrupt request

signal

Address

Write

TSR address

TSR write cycle

Figure 10.42 Timing for Status Flag Clearing by CPU

The status flag and interrupt request signal are cleared in synchronization with P

φ after the DTC or

DMAC transfer has started, as shown in figure 10.43. If conflict occurs for clearing the status flag

and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up

to five clock cycles (P

φ) for clearing them, as shown in figure 10.44. The next transfer request is

masked for a longer period of either a period until the current transfer ends or a period for five

clock cycles (P

φ) from the beginning of the transfer. Note that in the DTC transfer, the status flag

may be cleared during outputting the destination address.

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