H8SXSLASH1663 datasheet(628/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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制造商	RENESAS [Renesas Technology Corp]

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628 / 1158 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 576 of 1102

REJ09B0294-0100

10.10.5

Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence

and TCNT is not incremented. Figure 10.47 shows the timing in this case.

TCNT input

clock

TCNT

Address

Write

TCNT write cycle

TCNT write data

TCNT address

Figure 10.47 Conflict between TCNT Write and Increment Operations

10.10.6

Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence

and the compare match signal is disabled. A compare match also does not occur when the same

value as before is written.

Figure 10.48 shows the timing in this case.

TGR

Compare match

signal

TCNT

+ 1

Address

Write

TGR address

TGR write cycle

Disabled

TGR write data

Figure 10.48 Conflict between TGR Write and Compare Match

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