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H8SX/1663 数据表(PDF) 642 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 642 Page - Renesas Technology Corp

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Section 11 Programmable Pulse Generator (PPG)
Rev.1.00 Jun. 07, 2006 Page 590 of 1102
REJ09B0294-0100
• NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial
Value
R/W
Description
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
with PCR.
If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit
Bit Name
Initial
Value
R/W
Description
7
6
5
4
NDR7
NDR6
NDR5
NDR4
0
0
0
0
R/W
R/W
R/W
R/W
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
with PCR.
3 to 0
All 1
Reserved
These bits are always read as 1 and cannot be modified.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
All 1
Reserved
These bits are always read as 1 and cannot be modified.
3
2
1
0
NDR3
NDR2
NDR1
NDR0
0
0
0
0
R/W
R/W
R/W
R/W
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
with PCR.



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